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 [![pipeline status](https://git.iiens.net/brateau2015/diglog/badges/master/pipeline.svg)](https://git.iiens.net/brateau2015/diglog/commits/master)
 
-**IMPORTANT: We are not going to maintain this version of the code. The new project is under https://git.iiens.net/diglog**
-
 Log (diglog + analog) is a graphical environment for entering circuit
 schematics, and for analog and digital circuit simulation. Please see
 [previous README](README.old) for more information.